At its heart the AXIOM Gamma is modular, similar in design to a PC (different cards can be plugged in, swapped or replaced) Planned architectural choices and design: Many things outlined here are in the process of refinement and evaluation, this overview serves not as a set of results but rather show a current snapshot of the work-in-progress development.
The Pre-Processsing Module captures the raw image data from the sensor and is responsible for general “raw” processing of the sensel (image sensor pixel) values. This includes, for example, spatial and temporal binning of the raw data if lower resolutions and/or frame rates are desired in subsequent processing steps. Sensor access is implemented by using a Xilinx Kintex-7 160T FPGA, which also connects to the other modules via different IO types. To allow the capturing of short, slow motion sequences or for larger binning ratios, this module also features an external SODIMM-DDR3 (currently up to 8GByte) memory slot. This allows the sensor to run at its maximum frame rate (up to 300fps at full resolution) and fill the external memory. When the “burst recording” is finished, the data from memory can be processed at “normal” speed.
This is the “heart” of the camera where most of the actual image processing takes place. A platform of what is most likely to be a Zynq 7030 FPGA + dual ARM core System on Chip (SoC) - a higher power version of the SoC being used in the AXIOM Beta.
These slots are generally used for storage, input or output of high-speed signals. Typical examples would be SSD storage, HDMI/SDI output or SDI input (possibly with restrictions, currently under evaluation). For this reason, the HSIOMs have dedicated high-speed access to the preprocessed image data coming from the Pre-Processing Module and the processed Data from the Processing Module. Connections are typically 4 lanes, either connected directly or via a high-speed mux. The theoretically achievable data-rate would be 10Gbps per lane (the limit of the mux, allthough the FPGA transceivers are not much faster), but the practically reachable data rate will likely be lower depending on EMI-performance, power-consumption and board losses. For a 4K raw image stream, only a fraction of the theoretical speed is needed.
The fifth slot is an adapter module for multiple (stackable) Low-Speed-IO-Modules at the back-end of the camera. These modules have no high-speed access to the raw image data stream, but are connected to the Processing Module and the Pre-Processing Module via multiple LVDS lanes to allow medium-rate traffic (1-2 Gbps total shared across all LSIOMs). Typical examples for such modules would be Audio, Timecode, Trigger or Genlock inputs/outputs, Gyroscopes, Accelerometers and GPS modules.
The backplane contains the different interconnects between the modules: Pre-Processing Board, Processing Board and HSIOMs - which are connected via high-speed serial links. Additionally, all modules are connected to each other via a number of LVDS lanes for lower rate traffic. Other tasks of the backplane circuitry include the power consumption measurement and management of an external Battery and also hot-plug detection and powering of the modules. Last but not least, the Backplane contains a muxed JTAG interface to allow debugging of all add-on boards via a central connector.