We are located in the industrial co-working space: Factory Hub Vienna. To increase hardware production speed of the AXIOM Beta we are in collaboration with our hosts to utilize the in-house hardware manufacturing capabilities. This should allow us to focus more on development again and less on hardware manufacturing.
On the road towards shipping first AXIOM Beta Compact (ABCP) units we decided for the following stackup: MicroZed 7020 SOM, Power Board v1.0, Main Board v1.0, Dummy Interface Board, THT Sensor Frontend, Single HDMI, Single USB 3.0. The hardware for the more efficient (switcher based) Power Board V2 is available as prototype, but the software support is not complete yet and right now we don't know what the effect on the sensor will be as this requires extensive testing, so we don't feel comfortable integrating it into the ABCP right now. The USB 3.0 module is currently our main focus because, despite the hardware being complete and working, we are only able to achieve half of the expected throughput with the proprietary D3XX libraries provided by FTDI. The fact that FTDI doesn't support isochronous transfers doesn't help with reliability either, but we are currently investigating our options there. The hardware design for the V2 Interface Board has changed over time as newer and cheaper FPGA solutions became available, but the actual design has always been postponed for two reasons: 1. It looks like we can't build it with OSHPark standards as it requires plated vias and probably more than four layers. 2. Something more important came up... Keep in mind that the V2 Interface Board is not essential for general operation, just increases sensor read out speed. We are about to have a second set of cnc milled AXIOM Beta Compact enclosure parts produced with small improvements in pretty much every component.
Note that not everyone who received a kit has agreed to be published on this map.
The skeleton enclosure is the first mechanical design of the AXIOM Beta enclosure and especially intended for early adopters and developers as it does not actually enclose the hardware but rather hold it together. That way developers can easily access the hardware without disassembling it. The skeleton is milled from aluminum and coated in black. Since the hardware is fully exposed it is not suitable for outdoor operation.
Milled from several aluminum pieces and with different coating options the full enclosure should provide easy access to all connectors and interfaces while protecting the internal hardware with a solid metal shell. The full enclosure will have several modular parts held in place with metal screws. It will provide several 3/8” and 1/4” mount points in key places. Simple assembly and disassembly for access and repairability is of course also a goal.
This requires creating software that runs inside the camera to apply the corrections in real time in the FPGA (DSNU + PRNU) as well as software/methods for making the calibrations and verifying the results. Overcompensation can quickly make the image worse than before compensation so this will require some tweaking and optimising over time.
This requires software inside the cameras FPGA to run real time matrix color conversion (eg: white-balancing, offsets, channel merging, color effects, color space conversion) and developing the matching color profiling method with defined lighting and pre-measured color charts as reference.
Every image sensor has millions of pixels and a tiny amount is just statistically out of the expected response bounds or does not work at all - that’s normal and the missing value simple gets replaced by the average of neighboring pixels. This software takes care of this in real time and manages the positions/addresses of these dead pixels.
Canon, Nikon, MFT and Sony lens communication and control is planned where the actual features and implementations depend on the availability of protocol information and documentation and then on the success of reverse engineering anything that is not documented.
The background behind this idea is that that a raw image actually contains less data than a color image because with a bayer pattern image sensor not every pixel sees every color. The colors get reconstructed in the so called debayering process which typically happens in post production with raw footage. So in an RGB recording with 8 bits per channel we get 24 bits of space to park our data in for each pixel. Since most recorders do chroma subsampling eg. 4:2:2 that reduces the effectively available space to 16 bit per pixel. Now the trick is to just store a “monochrome” raw pixel in that space, two 12 bit raw pixels fit into one 24 bit RGB 4:4:4 pixel which would allow to eg. record twice the resolution or twice the frame-rate in a traditional 1080p datastream. If your recorder also supports the double frame rate (eg. 1080p60 if you aim for 1080p30) you actually get 4 times the bandwidth. 4K (or actually UHD) has four times as many pixels as HD, so voila that is the experimental 4K raw storage mode.
This of course means that the recorded video is not viewable out of the box anymore. Its not actually an image sequence you see when playing back the recording, its a visualization of a datastream. With the right interpretation (which any raw format needs anyway) all the original raw data can be utilized as raw footage. Initially this could be accomplished through a simple file conversion (ffmpeg, custom plugins etc.), and eventually (much sooner than later with community support), be widely adopted by NLEs and raw image/video processing software.
Currently the Sensor Interface Board is named “Dummy” because it's a very simple PCB that just forwards 32 of the 64 LVDS lanes from the sensor to the Microzed effectively limiting the sensor to 150FPS in 4K@10bit which is half it's capacity. The next generation of this board will feature an FPGA to interface all 64 LVDS data lanes and can also be utilized to preprocess the data - in the future this FPGA should act as a bridge between any future image sensor and the rest of the AXIOM Beta hardware. As 150FPS in 4K@10bit are already a lot of data and more than enough for the current application this task is currently low priority.
Currently the AXIOM Beta Powerboard reference voltages are set with trimmer potentiometers and the calibration process involves turning these with a small screw driver. New image sensors, shields or plugin modules could require different voltages though so the next generation of the Power board will be able to generate voltages as defined via software effectively paving the way for any future components implementation without having to use that small screw driver again.
Since the Camera is running Linux, you can use a simple Wifi dongle to access it. This allows low level access via SSH/FTP/SCP/etc. as well as operating high level Graphical User Interfaces via HTTP and any mobiles device’s browser.
The AXIOM Remote features push-buttons and switches as well as 2 rotary encoders (also with push-button function) that can be used to control a wide range of camera parameters like shutter speed, gain, overlays, FPS, gamma curves etc. .
Single PMOD debug inputs/outputs for connecting a wide range of external PMOD devices - mainly intended for development and testing when General Purpose Input/Output (GPIO) is required.
The 1080p60 4:4:4 output HDMI module is finished, the AXIOM Beta can accommodate up to two of these plugin modules and supply them with independent video streams.
Triple PMOD debug inputs/outputs for connecting a wide range of external PMOD devices - mainly intended for development and testing when General Purpose Input/Output (GPIO) is required.
Three independent DisplayPort Links act as diverse video output ports. Also supports adapters eg. to HDMI directly.
Allows recording 4K/UHD video on an external recorder with a standard 2160p signal. Will also work to supply 4K/UHD screens with a signal of course.
Offers 3.2 Gbit/s throughput which corresponds to 400MByte/s, enough to record uncompressed 4096x2160 raw 12 bit video at 25 FPS to a connected computer.
|design development hardware PCB||complete|
|develop preliminary 3G SDI output gear work||complete|
|design custom plugin module PCB||complete|
|develop 6G Litex gear work||in progress|
2x10 GPIO banks as LED indicators plus two power LEDs. 4 LVDS pairs routed to external connectors JP1/JP2 (plus one GND).